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Events

● SECURE-IC AT "C&ESAR 2011"

(28-30th November 2011, Le Triangle Hall, Rennes, France)

Secure-IC will be participating to the Computer & Electronics Security Applications Rendez-Vous. This year's topic of the Cesar conference is "Mobility & Security".

● SECURE-IC AT "JOURNEE AMBITION PME"

(November, 10^th 2011, UPMC Campus des cordeliers Paris)

As recently certified as "Entreprise Innovante" by the System@tic Paris Region competitiveness cluster, Secure-IC will be participating to the "Rencontres One2One PME-Investisseurs de la journée Ambition PME".

● SECURE-IC AT CARTES & IDENTIFICATION 2011

(15-17th November, Parc des Expositions Villepinte, France).

Secure-IC will be exhibiting, booth 4 K 136, its security evoluation tool, Smart-SIC Analyzer and the new generation of smartcard for the identification market, Smart-SIC+.

● SECURE-IC AT G20 YES 2011 (October 31^st - November 2^nd, Nice, France) As a member of the French delegation of entrepreneurs, Secure-IC will be participating to the YES G20 (Young Entrepreneurs Summit).The third edition of the G20 YES will gather 400 entrepreneurs from the 20 countries of the G20 on the theme "a new generation of entrepreneurs : builders of the XXIstcentury's economy".

● SECURE-IC AT THE ARTEA & ARTEMIS CO-SUMMIT 2011 (October, 25 & 26 2011, Helsinki Finland) Hassan Triqui, President of Secure-IC will be speaking at the "ICT Security" round-table.

● SECURE-IC AT MILIPOL 2011 (October 18-21, Paris Porte de Versailles) Secure-IC will be presenting its security evaluation tool Smart-SIC Analyzer at The Worldwide Exhibition of Internal State Security, hall 1 stand 2FO36.

● SECURE-IC AT LES RENDEZ-VOUS CARNOT (Lyon, France, 12-13 October 2011)

At "Les Rendez-vous CARNOT", the leading event in R&D for enterprises, Hassan Triqui, President of Secure-IC, will be speaking at the round table "To a world of Smart Devices" scheduled at 2:40 pm on October 12th, 2011.

● SECURE-IC AT CHES 2011 (Nara, Japan): September 28th - October 1st, 2011

At The Workshop on Cryptographic Hardware and Embedded systems, Secure-IC will be presenting its security evaluation tool, Smart-SIC Analyzer, that computes in real time extensive information theoretic metrics, and guides the system designer to efficiently cure them.

● SECURE-IC AT NIAT'11 (Nara, Japan): on September, 26th and 27th, 2011

At The Non-Invasive Attack Testing Workshop, Secure-IC will be presenting its security evaluation tool, Smart-SIC Analyzer, that computes in real time extensive information theoretic metrics, and guides the system designer to efficiently cure them. Additionnally, two technical talks on evaluation methodologies will be given: they put foreward respectively the interest of wavelets and of the stochastic models. Eventually, Scientific Advisor Sylvain Guilley will animate a round table about the DPA contests and its role to foster research towards better protections.

● SECURE-IC AT CARTES & IDENTIFICATION 2010 (Paris, France): on December 8, Scientific Advisor Sylvain Guilley will be speaking about a new design methodology to bridge the gap between security and evaluation using formal methods, where the countermeasure rationale is disclosed.
The security of smartcards relies primarily on their compactness and tamper-proofness. In addition, they embark a wealth of countermeasures against a large array of various attacks. Some of them are extremely focused and can even be intrusive. The fault injection and manipulation attacks are both known to be especially hard to resist against, because the attacker has an extremely high power.
The dominant strategies to thwart those attacks consist on regular monitoring of the card's integrity and on scattering, in space and time, of different checkpoints. It is of primary importance that the exact location of those checkpoints remains confidential; indeed, this way the attacker has a couple of chances to get through the detection but will be unable to reproduce the attack. This is all the more true as most countermeasures are probabilistic, in the sense that the checkpoints are not done always on the same variables or properties and not always at the same steps of the algorithms.
This tactic is indeed very efficient in practice; few attackers, even with advanced adaptative strategies, manage to succeed an attack by chance. However, it has two major drawbacks. First of all, it does not ensure the forward security of the product. Indeed, if a pirate finds a way to pass through the countermeasure(s) in a repeated fashion, then this information compromises all the smartcards equipped by the same active schemes of mitigation against active attacks. Second of all, the secrecy of the countermeasure details forbids any open-source evaluation of the smartcard. Indeed, as soon as the design of the card is exposed, it becomes trivial to attack between the defense lines.
See more on : http://fr.cartes.com/ExposiumCms/do/salon/CARTES+ID+FR/conferences/Programme/siteId_392053/pageId_1112456

● SECURE-IC AT SAME 2010 (Sophia Antipolis, French Riviera): on October 6, CEO Hassan Triqui will be part of the Start Ups panel. See more on: http://www.same-conference.org/index.php?option=com_content&view=category&layout=blog&id=119&Itemid=215

● SMARTEVENT'10 (Sophia Antipolis, French Riviera): on the e-Smart Program Day 2, Sylvain Guilley and Philippe Nguyen will be doing the presentation entitled "Smart-SIC Analyzer : a circuit level vulnerability assistant".

● AES An extensive characterization of dual-rail countermeasures, entitled "Evaluation of Power-Constant Dual-Rail Logics Counter-Measures against DPA with Design-Time Security Metrics" in the IEEE journal TC volume 59 issue 9, September 2010

● SECURE-IC AT CHES 2010 – At the Posters Session, Secure-IC will be presenting an extensive albeit computationally manageable leakage evaluation methodology of cryptographic accelerators. This methodology is the core of the Smart-SIC Analyzer evaluation environment. This tool provides the evaluator with an identification of the most leaking resources directly in the design netlist.

● WISA'10 (Jeju Island, Korea): Presentation entitled "Combined Side-Channel Attacks".

● FDTC'10 (Santa Barbara, CA, USA): Presentation entitled "Fault Injection Resilience".

● LATINCRYPT'10 (Puebla, México) Presentation entitled "Defeating Any Secret Cryptography with SCARE Attacks".

● EMC'10 (Fort Lauderdale, FA, USA): Presentation entitled "ElectroMagnetic Attacks Case Studies on Non-Protected and Protected Cryptographic Hardware Accelerators".

● CRYPTARCHI'10 (Gif-sur-Yvette, France): Three presentation entitled "Leakage Squeezing Countermeasure Against High Order Attacks", "The "Rank Correction" Technique to Improve Side-Channel Attacks" and "Pinpointing the leakage of dual-rail logics in FPGAs" (group picture).

● PASTIS'10 (Gardanne, France): Twain presentations entitled "Combined countermeasures against perturbation & observation attacks" and "Pinpointing the leakage of cryptographic circuits with an illustration on dual-rail logics".

● HOST'10 (Anaheim, CA, USA): entitled "Entropy-based Power Attack".

● AFRICACRYPT'10 (Stellenbosch, South Africa): Presentation entitled "Practical Improvements of Profiled Side-Channel Attacks on a Hardware Crypto-Accelerator".

● SOC-SIP'10 (Paris, France) : Presentation entitled "DPA et dérivées : Attaques et contre mesures".

● DTIS'10 (Hammamet, Tunisia) : Presentation entitled "Techniques for electromagnetic attacks enhancement".

● ICASSP'10 (Dallas, TX, USA) : Presentation entitled "Improvement of power analysis attacks using Kalman filter".

● DATE'10 in track A4 (Dresden, Germany): Twain presentations entitled "BCDL: A High Performance Balanced DPL with Global Precharge and Without Early Evaluation" and "Far Correlation-based EMA with a precharacterized leakage model".●

● CT-RSA'10 (San Francisco, CA, USA) : Presentation entitled "Unrolling Cryptographic Circuits: A Simple Countermeasure Against Side-Channel Attacks" (Slides).

● COSADE'10 (Darmstadt, Germany): Twain presentations entitled "Side-Channel Analysis based on Rainbow Tables" and "About Probability Density Function Estimation for Side Channel Analysis".

● ICECS'09 (Yasmine Hammamet, Tunisia): Presentation entitled "Updates on the Potential of Clock-Less Logics to Strengthen Cryptographic Circuits against Side-Channel Attacks".

● RCONFIG'09 (Cancún, Quintana Roo, México): Three presentations entitled "Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow" (IEEE, poster), "DPL on Stratix II FPGA: What to Expect?" (IEEE) and "White-Box Cryptography to Counteract SCARE" (IEEE).

● SCS'09 (Jerba, Tunisia): Two Presentations entitled "Evaluation of Countermeasures Implementation Based on Boolean Masking to Thwart First and Second Order Side-Channel Attacks" and "Overview of Dual Rail with Precharge Logic Styles to Thwart Implementation-Level Attacks on Hardware Cryptoprocessors".●

● CHES'09 (Lausanne, Switzerland): Presentation of the DPA contest results. This information is relayed via several press releases (alternative link) emitted by the TELECOM Institute.

● FDTC'09 (Lausanne, Switzerland): Presentation entitled "WDDL is Protected Against Setup Time Violation Attacks".

● HOST'09 (San Francisco, CA, USA): Presentation entitled "Security Evaluation of Different AES Implementations Against Practical Setup Time Violation Attacks in FPGAs".

● CYPTARCHI'09 (Prague, Czech republic): Twain presentations entitled "Evaluation of Countermeasures Implementation Based on Boolean Masking to Thwart Side Channel Attacks" and "Mid-term review of the 'DPA contest'".

● CRYPTOPUCES'09 (Porquerolles, France): Twain presentations in French entitled "Évaluation sur FPGA de contre-mesures aux attaques par canaux auxiliaires" and "Théorie de la corrélation multi-bit et rapport à mi-parcours du 'DPA contest'".

● DATE'09 in track A4 (Nice, France): Presentation entitled "Successful Attack on an FPGA-based Automatically Placed and Routed WDDL+ Crypto Processor".

● An IC cartography technique, entitled "ELECTROMAGNETIC RADIATIONS OF FPGAs: High Spatial Resolution Cartography and Attack of a Cryptographic Module" in the ACM journal TRETS volume 2 issue 1, March 2009.

● PASTIS'08 (Gardanne, France): Presentation entitled "FPGAs for Counter-Measures Evaluation".

● DCIS'08 (Grenoble, France): Twain presentations entitled "Security Evaluation of a Balanced Quasi-Delay Insensitive Library" and "A Secure Programmable Architecture with a Dedicated Tech-mapping Algorithm: Application to a Crypto-Processor".

● NTMS'08 (Tangier, Morocco): Presentation entitled "Fault Attack on AES FPGA Encryption Platform".

● FPL'08 (Heidelberg, Germany): Presentation entitled "Area Optimization of Cryptographic Co-Processors Implemented in Dual-Rail with Precharge Positive Logic".

● CHES'08 (Washington, DC, USA): Poster entitled "DPA Contest" and eponymous rump-session (One-year international contest, whose rules are available on: www.dpacontest.org).

● FDTC'08 (Washington, DC, USA): Presentation entitled "Silicon-Level Solutions to counteract Passive and Active Attacks".

● SSIRI'08 (Yokohama, Japan): Presentation entitled "Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs".

● FUTURE OF TRUST IN COMPUTING 2008 (Berlin, Germany): Presentation entitled "Shall we trust WDDL?".

● HOST'08, collocated with DAC'08 (Anaheim, CA, USA): Presentation entitled "Place-and-Route Impact on the Security of DPL Designs in FPGAs".

● CYPTARCHI'08 (Trégastel, France): Presentation entitled "Implementation and Evaluation of WDDL Countermeasures in FPGAs".

● EDCC'08 (Kaunas, Lithuania): Presentation entitled "Practical Setup Time Violation Attacks on AES".

● ARC'08 (London, UK): Presentation entitled "Physical Design of FPGA Interconnect to Prevent Information Leakage".