One-day tutorial with hands-on labs, 14/09/2018, Amsterdam (co-located with CHES)

Evaluating Security during IC-Design – Use Cases

Learn advanced analysis methods with Secure-IC experts, using Analyzr™, Virtualyzr™ and Catalyzr™ tools.

Program:

ISO/IEC 17825 test methodology

Vulnerabilities of hardware and software AES implementation

  • Correlation power analysis
  • Linear regression analysis
  • Collision attacks
  • Lab: analysis of an AES White Box Cryptography (WBC) implementation

Vulnerabilities of a software RSA implementation

  • Advanced post-processing for Timing/Horizontal analysis
  • Vertical Analysis
  • Lab: using machine learning techniques to extract a secret exponent

Vulnerabilities of Classical and Post-quantum Cryptography Implementation

  • Cache timing analysis
  • Static analysis of source code
  • Dynamic analysis of source code
  • Lab: patch vulnerability and re-chec

Date and Place:

September 14th, 2018 at Amsterdam (co-located with CHES)

Pricing:

Please contact us at contact@secure-ic.com.

Registration:

For further information, detailled program and registration, please contact us at contact@secure-ic.com or +33 2 99 12 18 72.