Advanced Trainings

  • There are four regular sessions per year
  • The four three scheduled sessions are:

27th to 29th June 2018

5th to 7th September 2018

21st to 23rd November 2018

  • Some custom sessions can be created from Secure-IC off-the-sheld courses or to explain a breakthrough topic; please inquire at contact@secure-ic.com.
  • For whom: designer of ASIC and FPGA solutions aiming at understanding security issues with respect to Software, Hardware and Mixed design.
  • Where? Secure-IC’s HQ at 15 Rue Claude Chappe, Bât. B, 35510 Cesson-Sévigné, France
  • Registration: For more information and special inquiries, please contact us at contact@secure-ic.com or by +33 2 99 12 18 72.

Program:

Day #1: Symmetric crypto analysis

  • AES with protections in software and in hardware (theory)
  • Known attacks: SPA, DPA, LRA, collision attacks, machine-learning, etc. (theory)
  • Pre-silicon analysis (lab)
  • Post-silicon analysis (lab)
  • Analysis of design improvement (lab)

Day #2: Asymmetric crypto analysis

  • RSA with protections, as a mixture of firmware + hardware arithmetic accelerator (theory)
  • Known attacks: SPA (conditional tests, extra-reductions, etc.), DPA, machine-learning (clustering), etc. (theory)
  • Pre-silicon analysis (lab)
  • Post-silicon analysis (lab)
  • Analysis of design improvement (lab)

Day #3: Microarchitectural attacks (cache timing, incl. Spectre, etc.)

  • Post-quantum algorithm (theory)
  • Known attacks: cache-timing attacks (theory)
  • Static and dynamic analysis (lab)
  • Analysis of design improvement (lab)
  • Wrap-up: feedback about the program & the tools, the balancedness between theory/design/evaluation, suggestion of new topics

 

Download the Flyer here.