Back-End Engineer

Secure-IC is a world-leading provider of embedded cybersecurity solutions, headquartered in Rennes, France with offices in Paris, Singapore and Tokyo (70+ employees).

Secure-IC recently achieved ten years in business of growth and progression, during which time the company has expanded globally. With presence in 20 countries across 5 continents, backed by almost 40 families of international patents, more than 200 scientific papers, Secure-IC has established a thought leadership position in the cyber security world for embedded systems.

We provide best in class protection technologies, integrated secure elements, with security evaluation tools for certification readiness and security assurance as well as consulting expertise and security assessment services. We protect companies against cyber-physical attacks and guarantee at each stage of the design process that the absolute optimal security level is reached.

Secure-IC’s solutions are delivered to the best technology companies worldwide with solutions used in millions of products such as smartphones, laptops and computers, automotive chipsets, smart meters, passports, etc.

 

Key Responsibilities

As a Design and Back-End ASIC Engineer, you will develop Secure-IC’s IP cores portfolio by ensuring the various phases of specifications, design, testing, integration.

You will take charge of the design of the IPs by improving the physical implementation flow (RTL to GDSII) and you will notably perform the following missions:

  • Floorplan, Placement-Routing, Synthesis of clock trees, Performance optimization (area, delays, consumption)
  • Physical implementation (RTL2GDSII)
  • Static Timing Analysis (STA)
  • Post-layout verification (DRC, etc.)
  • Development of timing constraints
  • Logical synthesis of the circuits developed by the digital design team
  • Develop and improve the design flow
  • Flow automation (TCL, Bash, Makefile)

You will also participate in the design and development of our dedicated IPs offering for cybersecurity.


Education, Experience & Skills Required

  • Master degree/Engineer Diploma in Microelectronics
  • Good knowledge of VHDL
  • Knowledge and previous professional experience in FPGA / ASIC design
  • Knowledge of the back-end flow (synthesis, routing placement)
  • Knowledge of ASIC-oriented design tools from Cadence “synthesis (Genus), PnR (Innovus) and verification
  • ignoff (tempus, caliber ..)
  • Knowledge of a file revision management tool is a plus (Git)
  • English language proficiency
To apply, please send only PDF. Word document won’t be opened.
  • Accepted file types: pdf.