VIRTUALYZR is an electronic design automation (EDA) software tool dedicated to pre-silicon security evaluation. The tool is easy to integrate within the design conception flow and allows a security check point at all design levels, namely RTL, Post Synthesis, Place-and-Route and Layout. Moreover, the analysis is end-to-end: from the design source, IP or SoC, to the full security report generation. Security vulnerabilities are extracted from any cryptographic, non-cryptographic or functional (bus, memories) implementation.


Two types of analysis are possible :

  • Black box-based analysis assumes that the secret is unknown and tries to recover the secret information. This allows measuring the extent of an attacker: how much time he needs to break the system. The Virtualyzr provides the last and powerful analyses existing for SCA and FIA.


  • White box-based analysis assumes that the secret is known and tries to focus on how such secret is behaving. In this context, the Smart-SIC Virtualyzr provides powerful metrics based on advanced statistical computation derived from the recent literature of physical analysis.



The high-level description of the internal process consists in three steps, detailed below.


  • Step 1

    The design is simulated according to its level conception (RTL / Post Synthesis / Place & Route). Simulated traces are obtained. The Virtualyzr allows the user to select and probe the nodes to be tested.

  • Step 2

    The simulated traces are investigated and processed based on a mathematical consumption model to generate the so-called leakage traces. These traces are an image of the security leakage that can be exploited by an attacker to retrieve a sensitive information like a secret key.

  • Step 3

    An advanced physical analysis is performed on obtained leakage traces. Two types of analysis can be performed: black-box or white-box analysis.