French Japanese Cybersecurity Intermediate Workshop 2021 – 25-26 Feb 2021
As part of the joint collaboration between France and Japan on Cybersecurity Research initiated in 2015, scientific workshops are regularly organized, in France and in Japan.
Due to the current sanitary situation, the 6th Franco-Japanese Cybersecurity Workshop to be held in Bordeaux has been postponed to September or October 2021. In the meantime, an intermediate online Workshop will be held online on February 25 and 26, 9:30-12:30 CET and 17:30-20:30 JST.
Secure-IC’s CTO Sylvain Guilley will give a talk on “Machine Learning based Hardware Trojan Detection using Electromagnetic Emanation”, on Feb. 26 at 10:10 (CET) or 18:10 (JST).
Below the abstract of his presentation:
The complexity and outsourcing trend of modern System-on-Chips (SoC) has made Hardware Trojan (HT) a real threat for the SoC security. In the state-of-the-art, many techniques have been proposed in order to detect the HT insertion. Side-channel based methods emerge as a good approach used for the HT detection. They can extract any difference in the power consumption, electromagnetic (EM) emanation, delay propagation etc. caused by the HT insertion/modification in the genuine design. Therefore, they can be applied to detect the HT even when it is not activated. However, these methods are evaluated on overly simple design prototypes such as AES coprocessors. Moreover, the analytical approach used for these methods is limited by some statistical metrics such as the direct comparison of EM traces or the T-test coefficients. In this paper, we propose a new detection methodology based on the Outlier/Novelty algorithms. This method, combined with the T-test based signal processing techniques, when compared with state-of-the-art, offers a better performance with a detection rate close to 100% and a false positive smaller than 1%. We have evaluated the performance of our method on a complex target design: RISC-V generic processors. The three HTs with the corresponding sizes of 0.53%, 0.27% and 0.1% of the RISC-V processors are inserted for the experimentation. The experimental results show that the inserted HTs, though minimalist, can be detected using our new methodology.
Registration online at: https://fj-cybersec2021.sciencesconf.org/index/index
If you are interested in our scientific publications, have a look at our Publications page.