Hardware Design Engineer

Permanent contract (CDI), based in Rennes.

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Your role and responsibilities

Within the Secure Silicon Engineering department, you will join a team of electronics and digital design engineers. You will be responsible for the development and delivery of IPs targeting FPGA and ASIC technologies. As an advanced developer, you will be actively involved in controlling and verifying the IP portfolio, in project planning, and in supporting and developing the team’s skills.

Your responsibilities will include:

Maintenance and improvement activities:

• Control of IP portfolio
• Migration of SVN IP repositories to GIT
• Analysis and fix of design / validation bugs
• Improvement of IP hardware scripts/environments
• Enhancement of existing functionalities
• Development and maintenance of internal tools
• Delivery of configurable or customized IPs
• Quality review of deliverables (peer review)
• Customer support

Design activities :

• Participation in defining IP architecture
• Analysis of specifications and standards
• Drafting of technical specifications
• RTL coding (VHDL/Verilog/SystemVerilog)
• Write internal and external documentation (doc, latex)
• Verification of code quality

Verification activities :

• Construction of functional test plan
• Construction of verification environment (VHDL or SystemVerilog testbench)
• Creation of IP verification models (SystemVerilog, python)
• Test coding and execution (non-regression) using RTL simulation tools (Questasim/Modelsim/Xcelium/VCS)
• Coverage analysis (code coverage / functional coverage)
• Verification report writing

Prototyping activities (FPGA):

• Development of synthesizable IP models for FPGA targets
• Support to Software and Integration teams

Pre-sales support activities :

• Support to pre-sales and architecture teams to meet IP creation/customization needs
• Technical referent at customer meetings
• Participation in estimating project loads
• Participation in drawing up specifications and defining requirement

Education, Experience & Skills

• Fluent English required (customer meetings)
• You have significant experience in RTL IP design flow (VHDL or Verilog/SytemVerilog) for FPGA or ASIC targets.
• You have between 5 and 7 years’ experience as a digital design engineer.
• You are familiar with a hardware description language such as VHDL or Verilog.
• From existing code, you are able to deduce the logic that will be synthesized in the circuit.
• You have significant experience in RTL verification (directed or randomized tests, VDHL testbench or System Verilog).
• You have experience in FPGA or ASIC synthesis (static timing analysis, writing timing constraint files).
• Scripts coding skills in a Linux environment (Makefile, python, shell, tcl…etc)
• Experience in security/cryptography is recommended
• Knowledge of UVM verification methodology is a plus
• Skills in embedded software are a plus
• You are rigorous, independent, organized, open-minded and proactive. You are also a good communicator.

Secure-IC is committed to equal opportunity and diversity. Our positions are therefore open to people with disabilities. Only skills and motivation make a difference.