Securyzr™ TLS Handshake Hardware Accelerator
Offloads the compute intensive public key operations such as signature generations and verifications.
The TLS Handshake Hardware Accelerator combines a load dispatcher and a configurable amount of instances of the Public Key Crypto Engine, benefiting from all features supported (i.e. RSA / DH / DHE and ECDSA / ECDH / ECDH E / X.25519 / X.448 and more).
The efficient dispatching to several tenths of Public Key Crypto Engine instances helps reaching maximum system performance.
WHY TLS Handshake Hardware Accelerator?
Huge reduction for cpu overhead & incredible improvement for work processing efficiency
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High scalability | |
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Trade-off between throughput, area and latency | |
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Optimal performance for any application regardless of the platform on which the solution is implemented | |
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Easy porting to ASIC and FPGA | |
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Support of a wide range of applications in cloud computing and data centers |
Features
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Scalable architecture | |
Wide variety of crypto algorithms supported: | |||
| • RSA with and without CRT | ||||||
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OpenSSL integration (optional) | • Elliptic Curve Cryptography(ECC) | ||||
| • Diffie-Hellman (D-H and ECDH) Key Exchange | ||||||
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Custom operations possible on request | • Digital Signature Algorithm (DSA) & Elliptic Curve | ||||
| • Digital Signature Algorithm (ECDSA, EC-KCDSA & EdDSA) | ||||||
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High performance on off-the-shelf FPGA | • X.25519/X.448 | ||||
| • SM2 | ||||||
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Plug’n Play integration with PCIe (e.g., Xilinx Alveo board) | • Any other crypto algorithm can be supported | ||||
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ASIC and FPGA (incl. UltraScale+ & Versal) |
Wide area of applications
The TLS Handshake Hardware Accelerator will make the cloud processing boards among the most efficient and flexible available, whatever technology and architecture you choose.
Environments in which the TLS accelerator will prove an essential boost are:
Algorithmic performance (OPS/S) with OpenSSL
Using OpenSSL v1.1.1G /OpenSSL speed command
SecuryzrTM TLS Handshake Hardware Accelerator
The TLS Handshake Hardware Accelerator IP core is easily portable to ASIC and FPGA. It supports a wide range of applications on various technologies. The unique architecture enables a high level of scalability enabling a trade-off between throughput, area and latency.
Built for your specific needs
The TLS Handshake Hardware Accelerator can be configured to reach the performance level required by your application, enabling efficient offloading of the main CPU.
Free white paper
HOW SMART & SECURE HARDWARE
CAN BOOST YOUR DATA CENTER
High-performance IP blocks to offload network and security processing
Cloud computing is ramping up like never before. New host applications are routinely designed to serve millions of clients, and each of these clients expects high-speed service, minimal latency, and tight security.
Learn more about the key components to boost your data center:
• Record-breaking MACsec performance (up to 1.5Tbps)
• The fastest SSL/TLS handshaking engines in the industry
• …and much more
The first worldwide PQC READY secure solution from chip to cloud
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At Secure-IC we are at the forefront of PQC, meaning we are actively working on developing and implementing PQC technologies, and contributing to the advancement of the field. We are conducting research, creating new PQC algorithms, developing PQC-based products, and working with customers to integrate PQC solutions into their systems. |
We are also offering Cybersecurity Evaluation Tools & Security Evaluation as a Service
